Reduced instruction set computers (RISC) recognize the advantages of employing a set of high-speed, general-purpose registers for the storage of often-used data in conjunction with a lower-speed main memory for the storage of less-frequently used data. Run-time studies of programs indicate that the data most often-used in procedures are typically simple, non-array variables, and not in excess of thirty-two such variables are used with a procedure. The Berkeley RISC machines RISC I and RISC II, the Stanford MIPS machine, and the IBM 801 are representative of RISC architectures.
At run-time, a stack is used in allocating and deallocating activation records whenever a procedure of a high-level language (HLL) is invoked or returned from, respectively. The activation record includes portions for incoming parameters (variables), purely local variables, and outgoing parameters (variables). The portion allocated to the outgoing parameters of one activation record of a procedure may be overlapped with the portion allocated to the incoming parameters of another activation record of another procedure so that parameter values may be efficiently communicated between the procedures.
A compiler for a HLL arranges data references within a procedure so that most references are to the high-speed registers to improve performance. RISC architecture machines contain a set of high-speed registers which exceeds the number required for the storage of often-needed data within any given procedure, for example, thirty-two registers. The Berkeley RISC machines assign a fixed number of registers to a procedure ("window"). Since this number is generally larger than that actually required by a procedure, waste of registers is inevitable.
Ideally, only the number of registers actually required by a procedure should be allocated for it and the registers in excess of those required could be used to store variables for communication between procedures, and for other tasks.